1. Field of the Invention
The present invention relates to an output buffer, and more particularly, to an output buffer for compensating a deviation caused by process variability.
2. Description of the Related Art
An output buffer including a CMOS circuit is used for a semiconductor circuit. FIG. 21 is a circuit diagram showing a generally-known output buffer. The output buffer shown in FIG. 21 is a buffer for inverting and out putting a signal applied to an input terminal. When an intermediate potential VDD/2 between a power supply potential (VDD) and a ground potential (VSS) is input to the input terminal of the output buffer, it is preferable to output the potential VDD/2 from an output terminal thereof. A technology of stabilizing the potential at the output stage is described in, for example, JP 2006-245828 A.
However, in an output buffer circuit 11 where a CMOS circuit is included as shown in FIG. 21, when a PMOS transistor and an NMOS transistor are formed, there exists process variability. As a result, when the characteristics of the respective transistors deviates from design values, an output voltage may deviate from VDD/2 even if the VDD/2 is input as an input voltage. Therefore, there is the case where the output buffer circuit 11 does not act as an output buffer which performs an accurate operation.
The output buffer circuit 11 according to the conventional technology includes an input terminal 11 to which an input signal IN is input, an n-type MOS transistor MN1 for generating an inverted logic of the input signal IN, a p-type MOS transistor MP1 serving as a load for the MOS transistor MN1, and an output terminal 2 from which an output signal OUTB is output.
The sizes of the MOS transistors MP1 and MN1 of the circuit as shown in FIG. 21 are generally determined such that, as an operating point (point at which the middle of the amplitude of a signal output to the output terminal 2 relative to a voltage input to the input terminal 1 is equal to VDD/2), a voltage VOUTB output to the output terminal 2 becomes VDD/2 when a voltage VIN input to the input terminal 1 is VDD/2.
However, a semiconductor circuit manufacturing process size has been reduced in recent years, so variations in current gain (β) value and threshold voltage (Vth) value in each of the n-type MOS transistor and the p-type MOS transistor are caused by the process variability as described above. Therefore, even when the semiconductor circuit is formed based on values obtained by theoretical calculation, there is a difference from expected transistor capability, so a predetermined circuit output is not obtained.
Here, a variation in transistor capability being caused by the variability of the manufacturing process (process variability) is expressed as “n-type MOS transistor capability/p-type MOS transistor capability.” For example, when the process variability is “large/small,” a current gain βN and a threshold voltage VthN of the n-type MOS transistor and a current gain βP and a threshold voltage VthP of the p-type MOS transistor deviate from expected values. Therefore, the operating point of the voltage VOUTB decreases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in FIGS. 22A and 22B. On the other hand, even when the process variability is “small/large,” the current gain PN and the threshold voltage VthN of the n-type MOS transistor and the current gain βP and the threshold voltage VthP of the p-type MOS transistor deviate from the expected values. Therefore, the operating point of the voltage VOUTB increases in the case where the voltage VIN is VDD/2. The operating waveforms at this time are shown in FIGS. 23A and 23B.
As described above, there is the case where the theoretical output corresponding to the input is not obtained in the conventional output buffer having the CMOS structure because of, for example, the process variability.